||Project Title: A Study of Mani-Core Programming Environment
1.Background and Motivation
The microprocessor is on the threshold of undergoing perhaps most significant transformation since the inception of the uni-processor chip, necessitating extraordinary advances and leaps in chip architecture and software design. Over the next decade, computer hardware and software technology (for both the high performance computing, as well as the embedded and personal computing markets) will undergo a revolutionary change.
The creation and migration of new workloads and usage models to mainstream computing will put enormous demands on future computing platforms, including much greater demands for increased performance, lower power consumption and increased functionality.
These seismic shifts in computer usage have called for a similarly dramatic change in the design of microchip architecture. It is increasingly clear that the large number of transistors that can be put on a chip – currently reaching 1 billion and continuing to grow (as followed by Moore’s Law) – can no longer be effectively utilized by traditional microprocessor technology that integrates only a single rocessor on a chip.
Intel has recently established “Platform 2015”, a long-term strategic plan towards a virtualized, reconfigurable chip-level multiprocessing architecture with a large number of cores. Speaking at the Intel Developer Forum in March 2005, Senior Intel Fellow Justin Rattner stressed that while new Intel multi-core chips – with 16 to 256 cores each will be cheaper to make and consume much less power, fundamentally new software must be developed to harness the full power of parallel systems and applications.A multi-core chip is essentially a multiprocessor system – a parallel computer by itself per se. The presence of multiple processors on a single chip brings along with it a new dimension of tasks that the computer system software has to handle, which an otherwise identical uniprocessor system would not have to worry about. With the advent of this multi-core rrevolution, there are fundamentally technology gaps that will need to be bridged in order for applications to take advantage of the massive pparallelism and high-performance features that multi-core architecture. This gap is reflecting in the parallel programming environment for such multi/mani-core chip architecture/systems: parallel programming models/languages, compiler and runtime technology and performance tools.
In this proposal, we will study programming environment for the emerging mani-core chip architectures and systems.
In particular, our study will be focused on the following areas:
(1) Study and compare emerging programming models and languages of the emerging mani-core chip technology with the
scalability of the traditional SMP based shared memory programming model. Such emerging programming models include bot
h the new programming languages based models (such as the high-productivity languages) and domain-specific languages
(such as Baker, etc.). We will also include a comparison study with other fine-grain multithreading models.
(2) Study and compare compiler optimization and runtime scheduling aspects for mani-core chips. Here, our emphasis
is event-driven asynchronous models -especially dataflow based models.
(3) Develop performance models and tools for performance evaluation of mani-core chip architectures and systems.
We will perform a simulation study based on simulation and execution of the selected workload on the chosen plat-
forms under this proposal. We will also leverage our expertise on compiler optimization for low power and multithread-
ing during this study. An experimental methodology will be developed for the target multi-core processor and the propo-
sed studies. Benchmark studies and workload analysis will be performed.